Design of Combinational and Sequential Circuits Using Cpld and Fpga

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Programmable Logic

Field-Programmable Logic

In Top-Down Digital VLSI Design, 2015

2.3.1 Simple programmable logic devices (SPLD)

Historically, FPL has evolved from purely combinational devices with just one or two programmable levels of logic such as ROMs, PALs and PLAs. Flip-flops and local feedback paths were added later to allow for the construction of finite state machines, see fig.2.6a and b. Products of this kind continue to be commercially available for glue logic applications. Classic SPLD examples include the 18P8 (combinational) and the 22V10 (sequential).

The rigid two-level-logic-plus-register architecture and the scanty resources (number of inputs, outputs, product terms, flip-flops) naturally restrict SPLDs to small applications. More powerful architectures had thus to be sought, and the spectacular progress of VLSI technology has made their implementation economically feasible from the late 1980's onwards.

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Programmable logic devices

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

11.13 Programmable logic sequencers (PLSs)

The essential features of a PLS are illustrated in the block diagram shown in Figure 11.23. In addition to the programmable AND and OR arrays provided on a PLA, the PLS has a number of on-chip single-bit memory elements which may be SR, JK or D-type flip-flops. In some cases, control of the flip-flops is available so that JK flip-flops can be converted to D-type flip-flops. Additionally, facilities are provided for latching the outputs.

PLSs are primarily intended for implementing synchronous sequential state machines of either the Mealy or the Moore type (see chapter 8). The flip-flop outputs represent the state variables of the state machine. Some of the flip-flop outputs are fed back to the programmable AND/OR arrays where they can be combined with the machine inputs to generate the flip-flop input signals. Other flip-flop outputs can be combined with machine inputs to generate the machine outputs. A clock signal is provided by an external source, and asynchronous preset and clear facilities for the flip-flops may also be available.

As an example of the use of a PLS, a hexadecimal counter will be designed. It will be assumed that the on-chip single-bit memory elements on the selected PLS are D-type flip-flops and the output of the counter will be decoded ready for directly driving a conventional 7-segment display.

The state table for the hexadecimal counter is shown in Figure 11.24(a). The inputs to the four flip-flops required for each state change are shown on the right of the state table, and have been obtained with the aid of the steering table for the D-type flip-flop shown in Figure 11.24(b). K-maps have been plotted and simplified for each flip-flop input in Figure 11.24(c), and the minimum form of the input equations obtained from them are

$\begin{array}{l} D_{D} = \bar{C} D + \bar{B} D + \bar{A} D + A B C \bar{D} & D_{B} = A \bar{B} + \bar{A} B \\ D_{C} = A B \bar{C} + \bar{A} C + \bar{B} C & D_{A} = \bar{A} . \end{array}$

The segment allocation for the seven-segment display is defined in Figure 11.25(a), as well as the segmental representation of each of the 16 hexadecimal digits. A truth table for the seven-segment decoder is shown in Figure 11.25(b), and the implementation of counter and display decode logic is shown in Figure 11.25(c).

Sixteen product lines are required for decoding the hexadecimal digits. As an example, the hexadecimal digit A (corresponding to the binary code 1010) requires that segments P, Q, R, T, U and V should be illuminated. Hence, for this binary combination, the signal for driving each of these segments must be set to 1, and the signal for segment S must be set to 0. The functions for all of the segments are easily read from the truth table. For example, the function for segment P is

$P = \sum 0, 2, 3, 5, 6, 7, 8, 9, A, C, E, F$

and the corresponding expressions for the other segments are obtained similarly.

As a further example of implementing a synchronous sequential machine using a PLS, consider the design of an invalid code detector for XS3 codes using a PLS with on-chip D-type flip-flops. Four-bit XS3 codes are fed to the detector, most significant digit first, and the machine is to be designed to give an active high output when an invalid code is received.

The ASM chart for the detector is shown in Figure 11.26(a). Since there are eleven states on the chart, four flip-flops (2⁴ = 16, 2³ = 8) are required to implement the machine. The column headed 'next state' in the state table (see Figure 11.26(b)) is a tabulation of the flip-flop input functions. These functions are relatively sparse (few 1s and 'don't care' terms compared to the total number of minterms), so they have been plotted on the reduced dimension maps (see sections 3.20 to 3.23) shown in Figure 11.27(a). After simplification, minimised excitation functions have been read directly from these maps and are written below the maps.

The output function Z has been plotted on a 5-variable K-map in Figure 11.27(b), and the following equations are obtained from the X = 0 and X = 1 maps respectively:

$\begin{array}{l} Z_{X = 0} = \bar{X} P S + \bar{X} P R + \bar{X} Q R S \\ Z_{X = 1} = X P S + X Q R + X Q R S \end{array}$

Combining these two equations gives

$Z = P S + \bar{X} P R + X Q R + Q R S .$

(Alternatively, the same result is obtainable from the equivalent reduced-dimension map for the output function, although with greater difficulty, because of the complex functions involved.) The PLS implementation of the invalid code detector is shown in Figure 11.27(c).

Manufacturers have also modified PALs to behave as PLSs by incorporating D-type flip-flops on the PAL chip. A typical example is the type 16R6 which provides 16 AND gate inputs and six rising edge-triggered D-type flip-flops, having a common external clock connection. The flip-flop outputs are taken to the external pins via tri-state inverting buffers having a common output enable signal (OE). When this device is used in the design of a synchronous sequential machine, the flip-flops (providing feedback to the AND matrix) can change state when the tri-state output buffers are disabled, as shown in Figure 11.28.

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THE BEL: A TEST BED FOR THE POSITIVE IONS BASED NEUTRAL BEAM INJECTORS WITH ENERGY RECOVERY SYSTEM FOR TORE SUPRA

P. Bayetti , ... G. Mayaux , in Fusion Technology 1996, 1997

2.4 Data acquisition and control system

The control and acquisition systems are standard industrial devices.

The control system is made up of four Programmable Logic Control modules (PLC) and field bus. Two PLCs are used for the control of the pumping systems, the rotating target, the gas injection and the chronology. The third PLC is devoted to the control of the Low Voltage P.S. The last one is connected to the general TS control network via a jbus optical link to control the High Voltage power supplies.

The data acquisition and processing system is made on two Personal Computers. The A.T.S. software controls the acquisition of 2×32 slow channels (down to 5 ms each) and 3×16 fast channels (down to 4 μs each). It performs 'on line' calculation facilities, easy signal display and data exportation to standard tools. After shot, data are transferred to the second P.C. for more sophisticated processing.

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Guidelines for benchmarking non-ideal analog memristive crossbars for neural networks

Alex James , in Mem-elements for Neuromorphic Circuits with Artificial Intelligence Applications, 2021

14.4.1 Programmable logic

The memristor crossbar can be used to build programmable logic gates. There are several ways in which programmable logic can be built with a crossbar. The best-known approach is by switching the resistance of the crossbar node to represent the data. There are several configurations that use this IMPLY [51], MAGIC [35], CNIMP [52], MRL [53], MAD [54], RTL [14], Scouting Logic [55] etc. They all can be used in a crossbar and often are assessed based on logic gate area, energy, and data latency. Almost, the majority of the memristor logic gates tend to outperform the CMOS-based logic gates. Among these gates, the threshold logic gates make use of neuron models for implementing the logic functions.

The memristor devices have much more variability than CMOS counterparts. This makes it necessary to test the performance of the memristor logic against the variability of the conductance. The device to device as well as the endurance becomes a significant issue for this. Another problem with many of the logic designs with memristors is the frequent need to change the resistance. The higher number of cycles are required to tune the memristor-based gates; their overall reliability becomes lower. The threshold logic gates have a high level of tolerance to device variability due to the ability to tolerate the variations in the weight values.

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FPGA Fundamentals

R.C. Cofer , Benjamin F. Harding , in Rapid System Prototyping with FPGAs, 2006

2.4 Summary

This chapter provided a high-level overview of the primary categories of programmable logic and the factors that affect PLD technology selection. The three PLD categories include SPLDs, CPLDs and FPGAs. The crossover between CPLD and FPGA applications was discussed. The overlap between the two technologies can be significant; however, for larger, more complex projects, FPGA technology provides many benefits. The primary types of FPGAs and major FPGA manufacturers were presented. The primary FPGA categories are OTP and SRAM-based. SRAM-based FPGAs are typically better suited for rapid system prototyping applications due to their reprogrammability and flexibility. Since SRAM-based FPGAs are well suited for rapid system prototyping, special attention was focused on the architecture of SRAM-based FPGAs. The structures introduced in this chapter will be referenced throughout the remainder of the book. Figure 2.21 illustrates the FPGA structures presented in this chapter.

The fundamental FPGA structures presented included the CLB and slice, routing matrix, global signals, I/O blocks, clocking resources and memory. The advanced features, including intellectual property, embedded processors, DSP blocks and advanced I/O will be presented in more detail in dedicated chapters later in the book.

This book uses the term slice to represent the lowest-level element within an SRAM-based FPGA. A slice is the fundamental element within an SRAM-based FPGA that is used to build larger logic structures. Slices may have different architectures within different families, even among FPGA devices from the same manufacturer. Alternative names for a slice include logic cell, macrocell, and logic element. The elements making up a slice include LUTs, flip-flops, dedicated logic and routing for connecting the elements. The LUT is a memory element used to implement any Boolean function with N or fewer inputs, where N is the number of inputs into the LUT. The number of inputs to the LUT may vary between manufacturer, family and device.

Manufacturers of SRAM FPGAs may also group slices into larger structures to form more complex logic blocks capable of providing a higher level of functionality. The name that is used for slice groups within this book is CLB. As with slices, the nomenclature, architecture, features, and size of these larger blocks may vary between manufacturer, family and device. Alternative names for CLBs include tile, logic array block and MegaLAB.

To build large logic structures, SRAM FPGAs use vertical and horizontal routing signals in a matrix arrangement that are paired with switch boxes at intersections to support FPGA element interconnection. These switch boxes or routing switches can implement both 90- and 180-degree routing connections. Switch boxes are located at the intersection of rows and columns and interfaces of CLBs and slices.

SRAM FPGAs interface to external circuitry via a ring of I/O blocks. These I/O blocks are referred to in this book as IOBs. Groups of I/O blocks can be collected into I/O banks. Individual IOBs have the ability to interface with a wide range of I/O standards, which can be selected by the FPGA designer. Available IOB standards may be limited based on the configuration of the I/O bank of individual IOBs. The primary FPGA element for handling, managing and adjusting FPGA local and system-level clocks is the CLOCK block. To provide improved margin timing within FPGAs, global and regional clocks should be utilized.

SRAM FPGAs have two primary types of embedded memory: distributed and block memory. Distributed RAM takes advantage of the memory-based structure of LUTs within the logic fabric; block RAMs are dedicated memory blocks placed within the FPGA fabric. The size and supported modes of operation for block memories may vary between manufacturers and device families.

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From the Ground Up!

Luis F. Chaparro , Aydin Akan , in Signals and Systems Using MATLAB (Third Edition), 2019

0.3.3 Field Programmable Gate Arrays

Another way to implement a digital signal processing algorithm is using field-programmable gate arrays (FPGAs) which are field-programmable logic elements, or programmable devices that contain fields of small logic blocks (usually NAND gates) and elements. The logic block size in the field-programmable logic elements is referred to as the "granularity" which is related to the effort required to complete the wiring between the blocks. There are three main granularity classes:

•: Fine granularity or Pilkington (sea of gates) architecture
•: Medium granularity
•: Large granularity (Complex Programmable Logic Devices)

Wiring or linking between the gates is realized by using a programming tool. The field-programmable logic elements are produced in various memory technologies that allow the device to be reprogrammable, requiring short programming time and protection against unauthorized use. For many high-bandwidth signal processing applications such as wireless, multimedia, and satellite communications, FPGA technology provides a better solution than digital signal processors.

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Overview of Embedded Systems Development Life Cycle Using DSP

Robert Oshana , in DSP Software Development Techniques for Embedded and Real-Time Systems, 2006

FPGA Solutions

An FPGA is an array of logic gates that are hardware-programmed to perform a user-specified task. FPGAs are arrays of programmable logic cells interconnected by a matrix of wires and programmable switches. Each cell in an FPGA performs a simple logic function. These logic funcctions are defined by an engineer's program. FPGA contain large numbers of these cells (1000–100,000) available to use as building blocks in DSP applications. The advantage of using FPGAs is that the engineer can create special purpose functional units that can perform limited tasks very efficiently. FPGAs can be reconfigured dynamically as well (usually 100–1,000 times per second depending on the device). This makes it possible to optimize FPGAs for complex tasks at speeds higher than what can be achieved using a general-purpose processor. The ability to manipulate logic at the gate level means it is possible to construct custom DSP-centric processors that efficiently implement the desired DSP function. This is possible by simultaneously performing all of the algorithm's subfunctions. This is where the FPGA can achieve performance gains over a programmable DSP processor.

The DSP designer must understand the trade-offs when using an FPGA (Figure 3.7). If the application can be done in a single programmable DSP, that is usually the best way to go since talent for programming DSPs is usually easier to find than FPGA designers. Also, software design tools are common, cheap and sophisticated, which improves development time and cost. Most of the common DSP algorithms are also available in well packaged software components. Its harder to find these same algorithms implemented and available for FPGA designs.

An FPGA is worth considering, however, if the desired performance cannot be achieved using one or two DSPs, or when there may be significant power concerns (although a DSP is also a power efficient device—benchmarking needs to be performed) or when there may be significant programmatic issues when developing and integrating a complex software system.

Typical applications for FPGAs include radar/sensor arrays, physical system and noise modeling, and any really high I/O and high-bandwidth application.

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Cyber-Secure and Resilient Architectures for Industrial Control Systems

André Teixeira , ... Karl H. Johansson , in Smart Grid Security, 2015

6.1.3 Illustrative Attack Case: Stuxnet

Out of all the malware threatening control systems, the one that sparked most amazement and concern was Stuxnet, not only because it was the first publicly known malware targeting ICS, but also due to its great complexity and functionalities. In the following illustrative case, we revisit some of the details regarding Stuxnet.

Stuxnet was discovered in 2010 and has been closely examined since then (Falliere et al., 2011). It is the first known malware tailored to compromise PLC software and it has raised several concerns due to its astonishing capabilities:

•: four zero-day exploits (flaws previously unknown to the software developers);
•: Windows rootkits (software to grant the malware with privileged rights and hide its existence from intrusion detection software);
•: first infection through USB drive;
•: infected devices can spread the malware through local networks;
•: peer-to-peer communication between infected devices;
•: self-update capabilities using the Internet and peer-to-peer communications;
•: remains dormant and continues spreading until a specific PLC software is found;
•: first known PLC rootkit;
•: ability to modify PLC software and hide the modified code.

Further analysis of Stuxnet shed light on its main goal and operation, from which plausible attack scenarios can be constructed. In particular, the attack scenario described in Figure 6.3 has allegedly occurred in reality (Kushner, 2013). This scenario illustrates the complex behaviour of Stuxnet and the potential damage it could have.

As concluded by Falliere et al. (2011), after a detailed analysis of the malware's capabilities and behaviour, Stuxnet contains several interesting features: a resourceful and knowledgeable adversary, who aims at covertly disrupting the physical system. Therefore, these features are considered in the attack scenarios discussed throughout this chapter.

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Trends in Low-Power VLSI Design

Tarek Darwish , Magdy Bayoumi , in The Electrical Engineering Handbook, 2005

Hardware–Software Codesign

Hardware–Software Codesign techniques target system-on-chip (SoC) design or embedded core design that involves integration of general-purpose microprocessors, DSP structures, programmable logic (FPGA), ASIC cores, memory block peripherals, and interconnection buses on one chip. Traditionally, a system is divided into hardware and software sections that are designed independently except for some common standards required for compatibility concerns, shown in Figure 5.15(A). With systems growing larger and power consumption becoming of great importance, a new wave came forth to consider the whole system design process and attempt to partition the various tasks of the system between hardware and software from the early stages of the design process to reduce many design problems, as indicated by Figure 5.15(B). These techniques attempt to find an optimal partitioning and assignment of tasks between software running on microprocessors or DSPs and hardware implemented on ASIC or FPGA for a given application. In Henkel (1999), a system-level power optimization approach that deploys hardware–software partitioning based on a fine-grained (instruction/operation-level) power estimation analysis is proposed that achieves up to 94% savings in energy consumption. In this approach, the system tasks are partitioned into software sections running on a general microprocessor core and into hardware sections implemented in application-specific cores to minimize the total power dissipation.

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The Fundamentals

Clive Max Maxfield , in FPGAs: Instant Access, 2008

SRAM-based Technology

There are two main versions of semiconductor RAM devices: dynamic RAM (DRAM) and static RAM (SRAM). DRAM technology is of very little interest with regard to programmable logic, so we will focus on SRAM.

Key Concept

SRAM is currently the dominant FPGA technology.

The "static" qualifier associated with SRAM means that—once a value has been loaded into an SRAM cell—it will remain unchanged unless it is specifically altered or until power is removed from the system.

How It Works

Consider the symbol for an SRAM-based programmable cell ( Figure 1-7 ).

The entire cell comprises a multitransistor SRAM storage element whose output drives an additional control transistor. Depending on the contents of the storage element (logic 0 or logic 1), the control transistor will be either OFF (disabled) or ON (enabled).

SRAM is currently the dominant FPGA technology.

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Design of Combinational and Sequential Circuits Using Cpld and Fpga

Source: https://www.sciencedirect.com/topics/computer-science/programmable-logic

Cofield Preclaid

Design of Combinational and Sequential Circuits Using Cpld and Fpga

Programmable Logic

Field-Programmable Logic

2.3.1 Simple programmable logic devices (SPLD)

Programmable logic devices

11.13 Programmable logic sequencers (PLSs)

THE BEL: A TEST BED FOR THE POSITIVE IONS BASED NEUTRAL BEAM INJECTORS WITH ENERGY RECOVERY SYSTEM FOR TORE SUPRA

2.4 Data acquisition and control system

Guidelines for benchmarking non-ideal analog memristive crossbars for neural networks

14.4.1 Programmable logic

FPGA Fundamentals

2.4 Summary

From the Ground Up!

0.3.3 Field Programmable Gate Arrays

Overview of Embedded Systems Development Life Cycle Using DSP

FPGA Solutions

Cyber-Secure and Resilient Architectures for Industrial Control Systems

6.1.3 Illustrative Attack Case: Stuxnet

Trends in Low-Power VLSI Design

Hardware–Software Codesign

The Fundamentals

SRAM-based Technology

Key Concept

How It Works

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